Integer Overflow Exploits Across Architectures: ARM, RISC-V, MIPS & PowerPC

Integer overflow bugs remain one of the most prevalent root causes of memory corruption and privilege escalation in low-level embedded C code. However, how microprocessors handle arithmetic wrapping varies fundamentally across architectures.

Architecture Comparison

• ARM (Cortex-M/A): Uses Dedicated APSR flags (C for unsigned carry, V for signed overflow). Conditional branches like BVS and BLO inspect these flags directly.
• RISC-V (RV32/RV64): Strips condition flags completely! Overflow detection requires explicit comparison instructions (e.g. ADD rd, rs1, rs2 followed by BLTU rd, rs1, overflow_handler).
• MIPS: The ADD instruction generates a hardware trap exception on signed overflow, whereas ADDU (unsigned add) wraps silently without trapping.
• PowerPC: Utilizes Condition Register (CR) and Summary Overflow (SO) bits in the XER register.